1. Field of the Invention
The invention relates to ordering cycles originating from multiple subordinate devices.
2. Description of the Related Art
Modern computer systems generally include input/output (I/O) devices that are connected to a central processing unit (CPU) via a system bus. The system bus operates to transfer addresses, data and control signals between the CPU and the I/O devices. Many modern computer systems include multiple buses, each in turn, with multiple I/O devices. Typically, any particular I/O device is coupled to only a single bus.
Bus bridges(bus-bridges) are often used in these multiple-bus systems to connect the multiple I/O devices connected to the multiple buses. “Bridge brides”(bridge-brides) are also often used in such systems to connect bus-bridges and thus handle communications from an even greater number of I/O devices. The commands transferred through both of these types of bridges frequently have data associated with them (e.g., read or write commands). The rate at which this multi-bridge architecture can process the communications generated from its multiple I/O devices directly affects the overall system performance. There is a constant demand for increasing the performance of modern computer systems generally. One way to achieve greater performance is to increase the rate at which communications from the I/O devices are processed.
As shown in FIG. 1, multi-bridge architectures can be viewed as having several different levels. A level 0 containing buses 122 and 124 and devices 112A–112F, which may be collectively referenced as 112, a level 1 containing bus-bridges 139 and a level 2 including bridge-bridges 149. Level 0 includes I/O devices 112 connected to buses 122 and 124. At level 1, bus-bridge 139 is connected to the buses 122 and 124 of level 0. Further, the bus-bridge 139 has a transaction order queues (TOQ) 131 and transaction buffers 186 for each bus-bridge/bus link, such as bus-bridge/bus link 162. TOQ 131 stores transaction buffer identifiers for certain transactions to ensure that system ordering rules, such as PCI and PCI-X ordering rules, are not violated. The purpose of the TOQ 131 is to ensure that transactions will execute in an order consistent with the system ordering rules. As such, not all transactions go into the TOQ, only those for which ordering rules apply. In contrast, transaction buffers store transaction information, such as cycle address, command, data, and the like. Next, level 2 contains one or more bridge-bridges, which may be represented by bridge-bridge 149. Bridge-bridge 149 is connected to one or more bus-bridges, such as bus-bridge 139 from level 1. Each bridge-bridge/bus-bridge link, such as bridge-bridge/bus-bridge link 152 between bridge-bridge 149 and bus-bridge 152, has one representative TOQ, which is TOQ 142, and one transaction buffer, such as transactional buffer 180, in the corresponding bridge-bridge 149. An inherent difference between bus-bridge 139 and bridge-bridge 149 is that bus-bridge 139 connect a series of buses 122 and 124, while bridge-bridge 149 connect a series of bridges. The bus-bridge's 139 direct link to buses 122 and 124 assures that bus-bridge 139 always know from which one of the buses 122 and 124 a transaction originated. Bridge-bridge 149, in contrast, does not have a separate link for each of the buses 122 and 124, and as such, are not inherently able to identify the bus source of any transaction. This inability to identify the bus source negatively impacts the ability for ordering transactions at the bridge-bridge level, and as such, also unnecessarily limits the corresponding transactional throughput of the entire system.
Transaction ordering, as discussed in more detail in the two U.S. patent applications incorporated below: U.S. patent application Ser. No. 09/749,111 by Paras Shah, “Relaxed Read Completion Ordering in a System Using a Transaction Order Queue,” filed Dec. 26, 2000, and issued into U.S. Pat. No. 6,615,295 on Sep. 2, 2003, and U.S. patent application Ser. No. 09/779,424, entitled “Enhancement to Transaction Order Queue,” filed Feb. 8, 2001, orders a set of transactions based on a predefined set of rules. These rules are designed to achieve optimum transaction ordering where a single TOQ receives transactions originating from a single bus. However, where a TOQ receives transactions originating from multiple buses, optimum transaction ordering is lost and the overall transaction throughput is reduced. In further detail, and as shown in FIG. 1, TOQs 142 and 131, are used in two different types of bridges in two different levels. The first bridge, in level 2, is a bridge-bridge 149, where single TOQs 142 are used per each bridge-bridge/bus-bridge link (child-link) 152, regardless of the number of buses 122 and 124 attached to the corresponding bus-bridge 139. The second bridge, at level 1, is a bus-bridge 139 where single TOQs 131 are used for each bus-bridge/bus link (grandchild-link) 160. In the case of a bus-bridge 139, where there exists a one-to-one ratio between TOQs 131 and 132 and buses 122 and 124, a TOQ 131, as designed, is limited to ordering the transactions from a single bus, and as such, is able to perform at its top design efficiency. However, in the case of a bridge-bridge 149, where there exists a one-to-many ratio between TOQs 142 to buses 122 and 124, a TOQ 142 is required to process transactions from multiple busses 122 and 124 over a single child-link 152. Specifically, TOQ 142 for example, is required to process transactions from multiple buses 122 and 124, and treat every transaction received through child-link 152, whether from bus 122 or bus 124, as though it originated from a single bus, and as such, the TOQ 142 is unable to function at its intended efficiency. In other words, because the bridge-bridge 149 is unable to discern between transactions of different buses 122 and 124 connected to a bus-bridge 139, the bridge-bridge 149 must order such transactions as though they occurred on the same bus, bus 122 for example. Because of this, unnecessary blocking occurs where a blocking condition on one bus, bus 122 for example, is imposed, across the entire child-link, child-link 152 for example, effecting every attached bus 122 and 124, and unnecessarily reduces transaction throughput.